Yosys
Yosys is a free tool that turns hardware design descriptions written in Verilog or SystemVerilog into circuit netlists that can be built into computer chips. It is intended for chip designers, engineers and researchers who work on digital hardware.
How hard it is to start using it. Easy: install it like a normal app, or use it in your browser. Advanced: you run it on your own server, use the command line, or it is a tool for developers.
Features
Circuit board layout
SourceNo
Circuit simulation
SourceNo
No commands needed
SourceNo
Ready parts library
SourceNo
Files for board makers
SourceNo
Chip design languagesVerilog well supported; SystemVerilog needs extra tools and licence
SourcePartly
Windows, Mac and Linux appCommand-line tool; builds and binaries listed for Linux; Mac via build steps
SourcePartly
Listed in
Covers chip logic synthesis only, not circuit board or analog circuit design or simulation.
How to help
AI contributionsNot stated
The project has not said how it feels about AI-written contributions. Maintainers can set this by claiming the listing.