Open Source Everything

Verilator

46ActiveLGPL-3.0

Verilator is a tool that runs computer simulations of digital chip designs written in hardware description languages. It is aimed at hardware engineers and programmers rather than everyday users.

Features

Circuit simulationSimulates digital chip designs only, not analog circuits
SourcePartly
Chip design languages

Listed in

Replaces partly

Simulates chip designs only; no circuit boards or schematics.

How to help

AI contributionsNot stated

The project has not said how it feels about AI-written contributions. Maintainers can set this by claiming the listing.

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